A variety of substantially planar electronic devices are known, comprising terminals and channels formed from a single layer of material, typically semiconductor material. Those known devices include diodes and other devices showing at least a degree of self-switching behaviour, logic devices and gates, and devices, such as planar transistors, with one or more side gate terminals, arranged adjacent a semiconductor channel, to which voltages may be applied to control channel conductivity and hence flow of current through the channel. Examples of such devices are disclosed in patent publications WO2006/008467, WO2006/120414, WO2002/086973, WO2010/049728, WO2010/013064, WO2010/086651, WO2011/027159, WO2010/013067, and WO2011/064575, the contents of which are incorporated herein by reference.
A problem with substantially planar electronic devices is how to manufacture them, with their various components or features correctly aligned with respect to each other, using as few process steps as possible. Particular problems occur when a mask or patterned tool is used at one stage of the manufacturing process, and then a second mask or tool needs to be aligned, at a later stage in the manufacturing process, with features produced using the first mask or tool. In other words, correct alignment of a plurality of masks or patterned tools to produce the requisite number of device or circuit features is a problem.
Further problems include how to manufacture small planar electronic devices, how to achieve small device features, especially on the nanometer scale, and how to produce substantially planar electronic devices and circuits incorporating them using as few process steps as possible and/or by grouping process steps so that the devices and circuits can be manufactured in a more efficient manner.
A further problem with certain known planar electronic devices is that their terminals (such as their source, drain, and gate terminals in the case of planar transistors) are formed from semiconductor material and hence have relatively low electrical conductivity. This can place constraints on terminal dimensions, can adversely affect the speed of the devices, and/or can reduce the efficiency of the devices.
A further problem with planar electronic devices is that certain terminals may be required to have large area, to facilitate the making of subsequent connections or interconnections to or between those terminals, and this requirement for large area can conflict with other device requirements.
A further problem is that certain techniques for the manufacture of planar electronic devices are incompatible with techniques for the rapid production of large numbers of devices, such as arrays of devices covering large areas.